List of Invited Talks

  • Bob Brennan, Samsung
  • Joonyoung Kim, SK Hynix
  • Naveen Muralimanohar, HP Labs
  • Mike O'Connor, NVIDIA and UT Austin
  • Tom Pawlowski, Micron
  • David Wang, Inphi

Program Schedule

  • 1:00-1:25: Bob Brennan, Samsung, New Directions in Memory Architecture
    Bio: Bob Brennan, a Samsung Senior Vice President, is leading Samsung's Memory System Architecture Lab or SALMemory Solutions Lab or MSL. MSL is chartered with leading the industry through the introduction of system and platform architectures that are aligned to the growth of Samsung's memory business. MSL also develops and enables world class products such as NVMe and PCIe Flash Drives. Prior to joining Samsung, Bob was the Lead Architect of Intel's Datacenter System on Chip products, with his most recent focus on Intel's Storage and "Microserver" line of products (codenamed Centeron, Briarwood, Avoton). Over the course of 22 years at Intel, Bob also led numerous design teams, including Notebook System Architecture, Mobile SoC Architecture, and Communication Architecture. Bob's educational background is mostly in computer architecture with a BSEE from Duke University and an MSEE from the University of Virginia.
  • 1:25-2:00: Tom Pawlowski, Micron, The Future of Memory Technology
    Abstract: Scaling of logic and memory technologies is becoming increasingly challenging. As we continue to scale, our challenges are compounded by new aberrations with each process node. Walls appear everywhere: locality, ILP, power, memory. And what of Moore? These issues are examined critically and a solution is proposed leading to an inevitable change in the way memory attaches into systems in abstracted form. This solution opens a new Pandora's box of opportunities. One such example is discussed: the new Micron Automata Processor built using memory technology.
    Bio: J. Thomas Pawlowski is a Fellow and Chief Technologist with Micron's Architecture Development Group. Mr. Pawlowski's experience includes the creation or co-creation of numerous groundbreaking memory architectures and concepts including: synchronous burst pipelined SRAM; hierarchical cache systems; Zero Bus Turnaround SRAM; the first double data rate memory (starting with SRAM and extending to DRAM and NAND technologies); PSRAM; high-speed NAND; the first double address rate memory; the first quad data rate memory; the first multi-channel memory; memories on SERDES buses; RLDRAM (the first DRAM to exceed SRAM performance); refresh and error correction schemes for memory subsystems; the architectural roots of Micron's HMC device; the first dedicated hardware architecture of Micron's newly announced nondeterministic Automata Processor; and other projects still in development. Mr. Pawlowski earned a bachelor of applied science degree in electrical engineering, summa cum laude, from the University of Waterloo in Canada. He has well over 100 U.S., international, and in-flight patents and serves on several advisory boards, including the Exascale Grand Challenge EAB. In his spare time, Mr. Pawlowski designs and builds loudspeakers and custom tools, and he has completed 60% of the design of a revolutionary electric car concept.
  • 2:00-2:25: Naveen Muralimanohar, HP Labs, Memristor Memory with Crossbar Architecture
    Abstract: As DRAM scaling is becoming more challenging, scalable alternatives with better cost per bit are being actively explored for future systems. Bipolar resistive memories such as Memristor enable us to explore a novel array architecture called crossbar, which changes many fundamental tradeoffs in memory design, and has the potential to provide high density. The talk will focus on Memristor crossbar and opportunities it provides to architects.
    Bio: Naveen Muralimanohar is a Senior Research Scientist at HP Labs, and his research focuses on memory system architecture for future servers. Currently, he is working on power efficient design of Memristor memories. He is the primary developer of CACTI 6.5 and has been maintaining it since 2008. He has co-authored a book titled "Multi-Core Cache Hierarchies". Naveen has been granted eight patents and has over 25 under submission. He received his Ph.D. in computer science from the University of Utah in 2009.
  • 2:25-2:35: Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling, Uksong Kang, Hak-Soo Yu, Churoo Park (Samsung Electronics, Korea), Hongzhong Zheng (Samsung Electronics, San Jose), John Halbert, Kuljit Bains (Intel), SeongJin Jang, Joo Sun Choi (Samsung Electronics, Korea). Slides
  • 2:35-2:45: Sparkk: Quality-Scalable Approximate Storage in DRAM, Jan Lucas, Mauricio Alvarez Mesa, Michael Andersch, Ben Juurlink (TU Berlin). Slides
  • 2:45-2:55: Improving Fairness in Memory Scheduling Using a Team of Learning Automata, Aditya Kajwe, Madhu Mutyam (IIT Madras). Slides
  • 3:00-3:30: Coffee Break
  • 3:30-3:55: Mike O'Connor, NVIDIA and UT Austin, Some Highlights of the High-Bandwidth Memory (HBM) Standard
    Abstract: The High-Bandwidth Memory (HBM) standard was recently finalized by JEDEC. This stacked-memory specification will enable significantly higher-bandwidth systems in the near future. This talk will present a brief overview of the HBM standard, focusing primarily on the interface with the host processor/memory controller. Aspects of the interface that are different than earlier DDR/GDDR memories, and some of the rationale for these new features, will be highlighted.
    Bio: Mike O'Connor is a Senior Research Scientist at NVIDIA where his research focuses on future GPU processor and memory architectures. Mike previously worked at AMD Research, where, among other things, he was involved in many aspects of the development of the HBM standard (including writing the initial draft specification document). Prior to AMD, Mike was in the product architecture group at NVIDIA where he was the lead memory system architect for several generations of NVIDIA GPUs -- including the first NVIDIA GPUs with GDDR5 support. Mike has also architected network processors at start-up Silicon Access Networks, an ARM processor core at Texas Instruments, and the picoJava cores at Sun. Mike has been granted 40 patents. He has a BSEE from Rice University and an MSEE from the University of Texas at Austin. Mike is currently working towards finishing his long-delayed PhD at UT-Austin. He is a Senior Member of the IEEE and a member of the ACM.
  • 3:55-4:20: Joon Young Kim, SK Hynix, Wide IO2 (WIO2) Memory Overview
    Abstract: To address ever increasing bandwidth needs while fighting off the challenge of signal integrity and other issues resulting from increasing pin speed, the memory industry has defined a new memory standard which has more pin counts. Wide IO2 (WIO2) is a strong candidate for future mobile memory solution which provides the bandwidth of up to 68GBps with only 1066Mbps of pin speed and many IOs (x512). Since WIO2 uses TSV technology to connect directly to the SoC, it achieves 30% power reduction compared to LPDDR3 solution, as well as smaller form factor as it is packaged together with the SoC. In this talk, we will give you an overview of the technology and contrast it with other products which use TSV technology.
    Bio: Joonyoung Kim (Joon) is Director of Product Planning at SK hynix America. He received his Ph.D in EE from University of Michigan and worked at Intel for 12 years where he designed multiple generations of Intel flagship CPUs. Joon has been with SK hynix since 2013 and works with key partners and customers to define next generation memory technology.
  • 4:20-4:45: David Wang, Inphi, Memory Buffer Devices - Why, How, and Examples
    Abstract: In this talk on memory buffers, we look at the reasons that memory buffers are used and look at the challenges in building the supposedly simple devices for on-DIMM memory buffering applications. We will then discuss the architecture of the DDR4 LRDIMM chipset in the context of these challenges. Then, we extend the discussion to cover other types of memory buffering for both on-DIMM and off-DIMM applications. Finally, we discuss some alternative memory buffers and future development paths of memory buffers.
    Bio: David is a Distinguished Engineer at Inphi Corporation. Currently, David is leading Inphi's efforts to develop high capacity, high bandwidth and energy efficient memory systems for server and workstation applications. David has co-authored a book on memory systems titled "Memory Systems: Cache, DRAM, Disk". Prior to joining Inphi in 2009, David was the lead memory systems architect for MetaRAM, working on buffered memory solutions for servers and workstations. David received his PhD from the University of Maryland in 2005, his PhD thesis is on the topic of a high-performance, power-constrained, DRAM-command scheduling algorithm.
  • 4:45-4:55: FaultSim: A Fast, Configurable Memory-Resilience Simulator, David A. Roberts (AMD), Prashant J. Nair (GaTech). Slides
  • 4:55-5:05: Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures, Prashant J. Nair (GaTech), David A. Roberts (AMD), Moinuddin K. Qureshi (GaTech). Slides
  • 5:05-5:15: Impact of Cache Coherence Protocols on the Power Consumption of STT-RAM-Based LLC, Mu-Tien Chang (U. Maryland), Shih-Lien Lu (Intel), Bruce Jacob (U. Maryland). Slides
  • 5:15-5:25: Area, Power, and Latency Considerations of STT-MRAM to Substitute for Main Memory, Youngbin Jin, Mustafa Shihab, Myoungsoo Jung (UT Dallas). Slides
  • 5:25-5:35: Fine-Grain Power-Gating on STT-MRAM Peripheral Circuits with Locality-Aware Access Control, Eishi Arima (U. Tokyo), Hiroki Noguchi (Toshiba), Takashi Nakada, Shinobu Miwa (U. Tokyo), Susume Takeda, Shinobu Fujita (Toshiba), Hiroshi Nakamura (U. Tokyo).