We invite short 4-page papers along the lines of IEEE Computer Architecture Letters. Papers should focus on the key new ideas and preliminary evaluations are fine. Accepted papers will be posted on the workshop webpage and should not preclude later publication at other conferences and journals. Approaches to memory management that rely on programming language techniques may be better suited to the SIGPLAN-sponsored MSPC workshop that is co-located with PLDI. An incomplete list of paper topics suitable for The Memory Forum is provided here:

• Novel DRAM architectures
• Usage of new memory interfaces (3DS, HBM, HMC, Wide IO, etc.)
• New memory technologies (PCM, MRAM, etc.)
• Usage of nonvolatile memory (analysis of benefits, performance, etc.)
• Hybrid memories combining multiple memory technologies or architectures
• Software management of main memory
• Memory scheduler and controller design
• Workload analysis focusing on memory performance
• Modeling and analysis of memory power and reliability

Submission site

Submission Instructions:

• Submissions are blind.
• Recommended paper length: 4 pages
• Recommended paper format: see the formatting templates for Computer Architecture Letters

Important Dates:

• Paper submissions due: Friday April 11th, 2014 (midnight Pacific)
• Notification: Friday April 25th, 2014
• Final Paper Due: Monday June 9th, 2014