WoNDP: 2nd Workshop on Near-Data Processing

In conjunction with the

47th IEEE/ACM International Symposium on Microarchitecture (MICRO-47)

Date: December 14th 1-5pm, 2014
Cambridge, UK


Maya Gokhale, Lawrence Livermore National Laboratory, Near Data Processing -- are we there yet?

Ravi Nair, IBM TJ Watson Research Center, Active Memory Cube: A Processing-in-Memory Approach to Power Efficiency in Exascale Systems

Robert Patti, Tezzaron Semiconductor, How 3D is Changing the Machine

Final Program:

Keynote Abstracts

Maya Gokhale, Lawrence Livermore National Laboratory
Near Data Processing -- are we there yet?
Abstract: Co-locating compute with memory to solve the memory bandwidth bottleneck has been a tantalizing dream for more than four decades. Novel processing in memory implementations have been designed, simulated, emulated, and even fabricated, but ultimately failed to become commercially viable. In recent years, increasing memory bandwidth pressure and power consideration provide renewed impetus to once again consider near memory computing to alleviate these problems. New packaging technologies that decouple memory from logic while maintaining high bandwidth offer a potentially viable tehcnical approach, but commercial viability remains elusive. In this talk I will discuss architectures and use cases for near memory compute that achieve performance and energy efficiency for broad ranges of applications including data center and deployed processors, potentially leading to commercial drivers suitable for widespread adoption.
Bio: Maya Gokhale is a Computer Scientist at the Lawrence Livermore National Laboratory (LLNL). Her career spans research conducted in academia, industry, and National Labs. She received a Ph.D. in Computer Science from University of Pennsylvania. Maya was a member of the Terasys project, which built a SIMD processing in memory SRAM chip in the early 1990s. Her current research interests include data intensive persistent memory architectures and reconfigurable computing. She is co-author of more than one hundred technical publications. Maya is a member of Phi Beta Kappa, a Distinguished Member of Technical Staff at LLNL, and a Fellow of the IEEE.

Ravi Nair, IBM TJ Watson Research Center
Active Memory Cube: A Processing-in-Memory Approach to Power Efficiency in Exascale Systems
Abstract: The cost of running a large-scale scientific computing system is increasingly being dominated by the cost of energy consumed. The Exascale initiative is targeting a power consumption of no more than 20 MW for a system capable of executing 10^18 floating-point operations per second to be deployed around 2020. This talk will argue the necessity of redesigning system nodes so that a part of the computation is performed close to memory in order to achieve this power-efficiency goal. A new architecture, the Active Memory Cube (AMC), will be described that places sophisticated computational elements on the logic layer below a stack of dynamic random-access memory (DRAM) dies. The vector architecture of the computational elements tuned to the requirements of a scientific exascale system will be described. The AMC ecosystem consisting of the programming model, compiler, and simulator will also be described, along with experimental results.
Bio: Ravi Nair is a researcher at the IBM Thomas J. Watson Research Center, where he has worked primarily in the areas of computer architecture, performance analysis, and design automation. He has co-authored a book with Prof. Jim Smith on "Virtual Machines". Ravi has a Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign, has spent a sabbatical year at Princeton University, and has also taught at Columbia University. His current interests include large-scale system design, processor microarchitecture, and approximate computing. He is a Distinguished Research Staff Member at IBM, a member of the IBM Academy of Technology, and a Fellow of the IEEE.

Robert Patti, Tezzaron Semiconductor
How 3D is Changing the Machine
Abstract: Moore's Law has been the future for 40 years, but the sun is setting on scaling. A new tool, 3D integration, is having a dramatic effect on the fundamentals of machine design and architecture. Rather than just adding transistor count, 3D provides "More than Moore" -- avenues whereby massive amounts of memory are effectively on-chip, increasing bandwidth by orders of magnitude. Much like Cray's innovative packaging that revolutionized early supercomputers, 3D integration opens new possibilities and re-imagines machine designs from the ground up.
Bio: Bob Patti is the Chief Technology Officer for Tezzaron Semiconductor. His recent work includes exascale targeted memory and memory sub-systems using photonic interconnect. Bob received the 2009 SEMI Award for his pioneering efforts in 3D integrated circuits. He is a member of IEEE and the former Vice-Chairman of JEDEC's DDRIII / Future Memories Task Group.