Note: Make reasonable assumptions where necessary and clearly state them. Feel free to discuss problems with classmates, but the only written material that you may consult while writing your solutions are the textbook and lecture slides/videos. Solutions should be uploaded as a single pdf file on Canvas. Show your solution steps so you receive partial credit for incorrect answers and we know you have understood the material. Don't just show us the final answer.
Every homework has an automatic penalty-free 1.5 day extension to accommodate any covid/family-related disruptions. In other words, try to finish your homework by Wednesday 1:25pm to keep up with the lecture content, but if necessary, you may take until Thursday 11:59pm.
An unpipelined processor takes 14 ns to work on one instruction. It then takes 0.2 ns to latch its results into latches. I was able to create a new pipelined processor by converting the circuits into 8 sequential pipeline stages. The stages have the following lengths: 1.6ns; 1.8ns; 1.4ns; 1.9ns; 2.1ns; 0.9ns; 1.7ns; 2.6ns. Answer the following, assuming that there are no stalls in the pipeline.
Consider a basic 5-stage in-order pipeline similar to the one discussed in class. How many stall cycles are introduced between the following pairs of successive instructions (i) for a processor with no register bypassing and (ii) for a processor with full bypassing? Use pipeline diagrams for each case to show if/how the second instruction is stalled.