Processor speeds continue to increase at faster rates than memory
speeds.  As this performance gap widens, it becomes increasingly
important to develop ``memory-conscious'' algorithms -- programs that
still optimize instruction count and algorithmic complexity, but that
also integrate optimizations for data locality and cache performance.
In this paper we present a topological isosurface extraction algorithm
which utilizes a ``cache-ring'' data structure to optimize memory
performance.  We compare our algorithm to an analogous edge-hashing
algorithm which, though functionally equivalent, gives less priority to
memory performance.  While our algorithm actually executes more
instructions during execution, we nonetheless see a speed-up over the
traditional method, as we more-than-compensate for the extra
instructions with superior memory performance.