The NSR Processor Prototype

		 William F. Richardson and Erik Brunvand

		 
			       UUCS-92-029

			       
		     Department of Computer Science
			   University of Utah
		      Salt Lake City, UT 84112 USA

		      
			     August 14, 1992



				Abstract

The NSR (Non-Synchronous RISC) processor is a general purpose processor
structured as a collection of self-timed units that operate concurrently
and communicate over bundled data channels in the style of
micropipelines.  These units correspond to standard synchronous pipeline
stages such as Instruction Fetch, Instruction Decode, Execute, Memory
Interface, and Register File, but each operates concurrently as a
separate self-timed process. In addition to being internally self-timed,
the units are decoupled through self-timed FIFO queues between each of
the units which allows a high degree of overlap in instruction execution.
Branches, jumps, and memory accesses are also decoupled through the use
of additional FIFO queues which can hide the execution latency of these
instructions. The prototype implementation of the NSR has been
constructed using Actel FPGAs (Field Programmable Gate Arrays).

This research was sponsored in part by NSF award MIP-9111793