We present a hardware description language (HDL) called hopCP
        for writing system-level specifications of hardware,
        and a simulation environment called CFSIM
        to validate hopCP behavioral specifications.
hopCP is a concurrent process-oriented HDL based on the
        Communicating Sequential Processes (CSP) paradigm with a few
        extensions: computations are specified in a purely functional style,
        and a restricted form of {\em distributed shared variables}
        are provided to support inter-process communication
        {\em without} synchronization.
hopCP addresses high level protocol modeling as well as low
        level signaling details.
A simulator in the CFSIM environment is generated by compiling a hopCP
        description into a Concurrent ML (CML) module.
This CML module can then be compiled using the native code generator
        of Standard ML (SML) and executed.
The salient features of CFSIM include the support for symbolic debugging
        via high level tester processes and the flexibility to
        support a wide variety of hardware specific constructs
        like barrier synchronization, multicast communication and
        non determinism conveniently via abstractions in SML.
In addition, the compiled nature of the simulator guarantees
        much more efficiency over interpreted simulators.
CFSIM is integrated with a hopCP-based high-level synthesis system for asynchronous
        circuits called SHILPA.

Note: This TR has been superceded by UUCS-92-001. Please see its
      .ps file and .abst.txt file.

      Also, a version of this TR has appeared in the
      "International Journal in Computer Simulation", 
      vol. 4, no. 4, pp. 375-394, 1994.